A large / fine - grain parallel dataflow model and its performance evaluation

Data driven architecture has been widely proposed in literature as an alternative to the von-Neumann design to handle real time and fifth generation applications. ,2 However, the network delays at the fine-grain dataflow level and handling of large arrays are some of the problems which should be addressed in these architectures. In this paper, we introduce a new model for dataflow computation which yields itself to an efficient realization of both static and dynamic dataflow architectures. Furthermore, the proposed model provides grounds for efficient handling of arrays in an SIMD fashion. Some implementation issues, the VLSI constraints, and architectural support for the model are discussed. The proposed organization achieves parallelism at the program block level (large-grain parallelism), instruction level (fine-grain parallelism), and data level (array processing). The system behavior is studied through a probabilistic simulation model and the conclusions are presented. * This research was supported in part by the Department of Defense under Contract 5-25089-310